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Hardware Architecture
Projects.

5-Stage Pipelined RISC-V Processor
Hardware Architecture

5-Stage Pipelined RISC-V Processor

Synthesizable RV32I processor in Verilog with IF, ID, EX, MEM, and WB pipeline stages, plus forwarding, load-use hazard detection, and branch/jump handling. Validated through simulation, synthesis, and FPGA implementation using Xilinx Vivado and an Artix-7 platform.

VerilogFPGAArchitecture
Single-Cycle RISC-V CPU
Hardware Architecture

Single-Cycle RISC-V CPU

Verilog RTL implementation of a single-cycle RV32I processor integrating the PC, instruction/data memory, register file, control logic, immediate generation, and ALU datapath. Simulated using Xilinx Vivado as a practical digital-design and computer-architecture project.

VerilogRTL DesignDigital Logic
Hardware Vision Accelerator
Hardware Accelerator

Hardware Vision Accelerator

Real-time SystemVerilog Sobel Edge Detector using FPGA Block RAM for high-speed image processing. Features optimized memory architecture and pipelined computation for efficient edge detection in hardware.

SystemVerilogFPGAImage Processing